Product Summary

The HY57V561620 is a kind of 268,435,456bit CMOS Synchronous DRAM. It is organized as 4 banks of 4,194,304x16. It is intended for the main memory applications which require large memory density and high bandwidth. The device offers fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Parametrics

Absolute maximum ratings: (1)Ambient Temperature, TA: 0 to 70℃; (2)Storage Temperature TSTG: -55 to 125℃; (3)Voltage on Any Pin relative to VSS VIN, VOUT: -1.0 to 4.6 V; (4)Voltage on VDD relative to VSS VDD, VDDQ: -1.0 to 4.6 V; (5)Short Circuit Output Current IOS: 50 mA; (6)Power Dissipation PD: 1 W; (7)Soldering Temperature × Time TSOLDER: 260 × 10℃ × Sec.

Features

Features: (1)Single 3.3V 0.3V power supply; (2)All device pins are compatible with LVTTL interface; (3)JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch; (4)All inputs and outputs referenced to positive edge of system clock; (5)Data mask function by UDQM and LDQM; (6)Internal four banks operation; (7)Auto refresh and self refresh; (8)8192 refresh cycles / 64ms; (9)Programmable Burst Length and Burst Type: 1, 2, 4, 8 and Full Page for Sequential Burst; 1, 2, 4 and 8 for Interleave Burst; (10)Programmable CAS Latency ; 2, 3 Clocks.

Diagrams

Image Part No Mfg Description Data Sheet Download Pricing
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HY57V561620B
HY57V561620B

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Data Sheet

Negotiable 
HY57V561620B-I
HY57V561620B-I

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HY57V561620C(L)T
HY57V561620C(L)T

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HY57V561620C(L)T(P)
HY57V561620C(L)T(P)

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HY57V561620CT-H
HY57V561620CT-H

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HY57V561620FTP-H
HY57V561620FTP-H

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HY57V561620FTP-H-C
HY57V561620FTP-H-C

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HY57V561620HLT
HY57V561620HLT

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Data Sheet

Negotiable